Electronics - Noise Cancellation
I have covered noise, electromagnetic field radiation minimisation using good component placement and PCB layout with short straight tracks for power switching and small signal input paths.
For example, separation by distance and screening of; signal, power, power switching, filter and Input/Output in a switch mode power supply.
Consider phasing of wound component - you can use a horizontally and vertically wound components placed to some degree will null each other's magnetic fields. There is some benefit in doing this, but there are not many wound magnetics with mounting options in all three planes, and in any case surface mount (SMT) flat pancake style wound parts when assembled are physically more robust.
The better method of placing wound magnetics is to keep a distance between magnetic parts and also keep distance between magnetic parts and the enclosures.
Keep a distance between signals and magnetic parts if necessary, use a screen can on a PCB,
Rout wiring away from magnetic parts such as switch mode power supplies - the strongest fields come from the inductors
And use mu-metal for low frequency screening such as motors.
Use ground planes so that signals finds the best return path which will be close to the signal path at higher frequencies.
Use transmission line approach with input and/or output resistors even for lower frequencies.
To minimise RF coupling,
To minimise differential noise with DC signals.
I also mentioned that a circuit design that charge injection (fixed pattern noise) can, to some extent, be used to cancel noise. Noise cancellation may be applied to remove fixed pattern or thermal noise, but this approach will add random noise. I have included some specific examples. These examples are not real, but the methods are used.
The picture right is a Hamamatsu N-MOS linear image sensor. It is a scientific quality linear image sensor similar to the commodity CCD linear image sensor used in bar code readers. There are two outputs, they are; pixel recharging current (pulse) from the image sensor and the other output is; dummy image sensor recharge current. The dummy signal is subtracted from the image signal to remove clocking noise and thermal noise. There is a design consideration whether you use the noise cancellation dummy video output or not, this approach is likely to add random noise?
These linear image sensors do not use a CCD, but the photo diodes and dummy diode are connected to two buses in turn as it is clocked. They are N-MOS can work with very high light levels and then achieve a very wide dynamic range, of 65,000:1 I think? It can be read in at a low data rate and still have a fair dynamic range and better light sensitivity. These are not the companies highest performing CMOS type.
A Toshiba CCD linear image sensor will work with much lower light level, higher temperature but depending on the clocking rate may have a dynamic range of up to 500:1. For example TCD1304 I've paired consecutive photo diodes to remove any odd/even diode non-uniformity, although the parts are very accurately made.
Reticon P-MOS and Fairchild CCD developed the first of these two types of image sensor in about 1970. Others were also developed in the UK at this time. The Reticon P-MOS linear image sensors had a four phase clock and I averaged four pixels in order to remove fixed pattern noise and once again the dummy video signal was not used, but a dark, reference and signal level chopped light system was used.
Older circuits tended to have low component count, particularly very few active components but use elegant design for noise cancellation that would have required a lot of work to optimise the circuit. I have illustrated with some valve circuits below, but a modern two transistor push-pull output or differential input is better and does not require so much component tuning, e.g. component matching;
The radio frequency valve amplifier show above has a screening mesh (pins 2 and 7) in addition any mains 50Hz coupled from the heater supply is cancelled by setting the potentiometer VR1 (it is called a hum dinger). Input and output resistors R2, R3 represent transformer windings circuit impedance normally with this radio frequency valve. (AL-0010-01A).
I had not attempted to properly design a valve amplifier stage including doing the maths as well before;
- The design method is as straightforward as is using modern SI units and designing a transistor amplifier stage.
As a teenager I would copy a standard design with variations then learn from my mistakes now I model before making anything.
Because of the use of a pentode valve with two screen grids the miller capacitance is very small, typically the Anode to Grid capacitance at 0.05pF (Cga). By comparison, any transistor will have a much higher miller capacitance. The Anode resistance is approximately; 92K = 100K // 1.25M (ra). And therefore the voltage gain is about 150 = 92K * 1.6mA/Volt (gm). What is unique about a pentode valve is the low miller capacitance - capacitance increased by the effect of the devices' amplification. Other capacitances are in the order of 5pF which is comparable with a small high voltage transistors selected for those parameters e.g. ZTX458. Cg mentioned above multiples by the gain of 7.5pF = 0.05*150 compared with the particular transistor which is 100pF. Note that the units used are old imperial ones not SI units, in this case there is no difference in how easy one either is to use. With the input driven from low impedance and resistors shown, the rise time to 63% is about 1uS. Other higher voltage valves would be comparable, but I do not have the capacitance figures for those or date on ideal types for such applications, but PL500 also looks promising instead of the transistor solution that I used in my oscilloscope long ago.
The audio output transformer shown in the valve amplifier See right has a mains hum cancelling winding, a technique commonly used in lower priced valve radios such as the Ultra Radio on a previous page. (AL-0010-02B) Both this and the circuit above were created using OrCAD Capture 16.6 the part valve on the right is not a part but drawn using curves, lines and buses which this tool has a very good selection of tools for creating those. The rectifier is likely to be a valve providing half-wave ratification.
Although a pentode valve's miller capacitance is much lower than any transistor type, I do not advocate the use of valves. Similarly, for a decade after Germanium (from about 1976) transistors were withdrawn there was no cheap alternative for a very low loss mains frequency inverters. In any case, such simple inverter designs would not comply with modern power quality standards. Cold cathode valves that did not require heaters were demonstrated in the 1970s, but too late. Philips were the last big manufacturer of valves but ceased making them in the 1980s. The drawback with valve type such as particle sensors is their susceptibility to electrostatic, electromagnetic fields and vibration called micro-phoney. Multiphase switch mode power supply
There are no real parameters defined in the diagram, and it is incomplete but is adequate for discussion of design issues.
When Vout+ is twice Vin+ and therefore the duty cycle of the PWM drive is 50:50 and then the current ramps in the two power inductors cancel each other.
See page 15..... of the data sheet link below for a good explanation of multiphase buck converter. A feature of this topology is the small capacitor in the output which means the design could be used for switch mode amplifier e.g. TEC (Pelter effect device) driver say?
The link to Renesas website changes, so I do not know if the data sheet Intersil can be found; isl6398.pdf
The circuit below is usually for a step-down synchronous buck, but the power transfer can be either way, so what is called Vin+ and Vout+ can be transposed that is either input or output power. (AL-0006-01C) Created using CADSTAR.
An effective method of minimising emissions and reducing the risk of damaging semiconductors is to use some form of snubbing. Snubbing reduces ringing and overshoot during switching transitions due to leakage or stray inductance. Snubbing lowers the Q of parasitic or leakage inductance. Snubber network R+C looks like a damping network or a control loop stabilisation network, and that is more-or-less what it does.
Making the gate series resistors a higher value than normally optimal will both cause a reduction in efficiency, but is a very effectively method of snubbing. This method is good for where the power supply efficiency is not important and extra heating (that in any case could still be modest) is not an issue.
Add the damper networks (R3-C6, R7-C13, R5-C8 and R8-C15) this method is very good and there is a different variant for converters with a single transistor that includes a diode. The diode is fitted across the resistor and the resistor value is higher.
The snubber in the power supplies can be interchanged for a suitable low Q capacitor and I have found Rifa-Evox X class capacitors very good, although they may have changed since I discovered that 30 years ago when prototyping a mains voltage SMP on veroboard. I do not know if alternatives are available, but the circuit require is R+C in parallel with C. Note although capacitors such as Polyester types have higher dielectric absorption so present a lower Q the Q of those types is still quite high and the R+C combination does it well.
An additional or other strategy would be to add Schottky diodes across the output transistors, these are fast enough to catch leakage inductance spikes cleanly compared with the substrate diodes in the transistors which are not good because they are likely to be slow in switching. Using slower diodes results in overshoot that is difficult to avoid in high voltage applications where Schottky diodes are not available.
I have added a gate driver IC. It is an unnecessarily high voltage type, but unfortunately it is also a higher gate drive voltage type at 10-20V. Both switching losses and consequently emissions due to the gate driver would be higher than is necessary using this particular IC. Another IC can be selected, this one is just a placeholder until better is found. On the positive side the driver is placed on the PCB very close to the transistors which will reduce emissions due to the gate drive.
This gate driver IC (2EDL05N06 Infineon) has a delay both and also interlocking to ensure that both transistors are not switched on simultaneously.
If you chose a gate driver that does not have delay do not put a diode across the gate series resistor, but you can put a Schottky diode and R.C.R network on the input to the driver because that input has a Schmitt trigger and this would be a less compromising fix. A logic solution would be tidier.
The input and output are decoupled and filtered with both high frequency type NPO/COG ceramic and a lower frequency high value ceramic capacitor. The design is likely to be improved by connecting 1nF COG/NPO type capacitors between Vin+ and Vout+ for each of the drivers. But these capacitors both are good and bad at different frequencies and are the only type that work in the VHF band.
The PCB layout has been optimised for short straight tracks around the switching transistors. You will see an oblong foil plan;
The power foils are formed of copper pour areas.
Both Vin+ and Vout+ have long track lengths. Although the high frequency decoupling is very short. This should be fairly optimal.
Two more inner layers could be added to this board, carrying Vin+ and Vout+ respectively. That would stiffen those rails and reduce AC differentials and therefore emissions potentially?
For four phases this lay out could be copied, rotated 180' and pasted. This would keep the power tracks short, but that could put the optimum connection point in the centre of the board - DO NOT DO THAT. Wiring crossing over power inductors is usually a very bad EMC strategy. BUT DO bring the power to the edge of the board - this looks reasonable with this layout plan and probably will work out best.
Add a lot more via's for 0V, for example. The power and switching copper areas do not have thermal relief so, to further electrically stiffen those nets. Without thermal relief's hand soldering such as for any rework will be difficult though but this difficulty is necessary.
My proposal for using a multiphase buck converter design but as a boost converter would require that the high and low side PWM (pulse-width-modulator) outputs be transposed on the controller IC. In that way I would expect the protection remains effective, but that would need to be checked.
Thermal management - the thermal pad is larger than required on each transistor. If this is insufficient add a similar pad to each copper layer and place many vias through. If the vias are placed under the transistors ensure that the paste mask is increased in size to load more solder and ask the PCB manufacturers/assemblers advice. Adding vias to under the mounting pad of the transistor will require a lot more solder.
Thermal areas and EMC - increasing the pad size will increase the area of metal and electrostatic coupled would be higher. In addition, mount the PCB on to an aluminium sheet with thermal electrically insulating pad. Place plenty of metal screw 0V bonding points around the board and perhaps in the centre as well, this should mitigate the electrostatic coupling issue I raised.
Refinements to the PCB layout; - The problem with this PCB layout is that you want the power input and the power output as close together as possible but that does not look possible. Perhaps if the board were re-laid out but with more copper layers and the two, four or many power stages arranged in a circle, with opposite phases next to each other, the power output and the power input all from the centre then potential switching noise would be reduced. Such a PCB could form an electrical switching noise null or minimum at the centre of the PCB, but may not be convenient for connection and the objective compromised if wire then ran near the switching chokes. In any case it is important to ensure each power stage is good in itself at the highest frequencies.
Similar strategies are also used by motor drive manufactures to balance the current between three phases, draw power from the mains but with good power factor;
I have seen a block diagram for an ABB motor drive for Micro power generation such as a wind turbine, water turbine and the diagram is much the same as for any industrial use. A use where spinning machines are slowing and speeding up and regenerative power is passed between those machines on a high voltage 700VDC bus. Surplus power can be returned to the grid using the three-phase power factor unit because it works similarly to the multiphase synchronous converter in either direction. I guess a motor drive or mains power factor / power inverter are all the same 3 half bridge drivers but with different firmware. These motor drives additionally have a power dump to dissipate power that can not be returned to the mains (because of the supply agreement or because there is plenty of power in the mains supply anyway)
Boost converter used for Power Factor Correction;
This circuit is fairly standard and similar to the circuit linked to and PCB layout I have shown previously Mechanical Design for good RF Performance for a boost or fly-back converter, but that case was for automotive LED lighting.
D1 of figure 2, I think, is fitted to ensure that the choke does not start up with the core saturated or the PTC switched open due to the power on surge charging the output capacitor and the load was occurring. Which a comparatively large value of inductor selected the circuit would not have large switching transitions between on and off because the current is flowing continually.
There is another variant of PWC controller, but that drives two transistors 180' out of phase and possibly could be used with the synchronous boost converter configuration show above to create a very low emission at double the input voltage. This is a fairly academic idea, but perhaps could be practical as a fly-back synchronous converter for battery charging? Texas Instruments make such PFC controller ICs they are called Interleaved PFC. The drawback is that this configuration is fly-back and the beneficial ripple cancellation would only be occurring when the mains voltage waveform is near maximum, which is in any case when it would be most significant.
If isolation is required use add a secondary winding to the switching inductors and place the output synchronous rectifier there.
There is a risk with this synchronous boost or buck where it is used with energy storing such as battery charging or DC motor drive. That is that if the output voltage is set lower than the actual voltage on the output pins power will be transferred back to the primary and could cause over voltage in the primary side. This is possible if a soft start feature is used. As part of the solution a fail-safe detector of such an over voltage condition that turns off all drive transistors should be included. The initial drive level applied by setting the PWM to the ratio of input and output voltage and then turning on a that setting before adjusting from there - this is significant added complication unless a microprocessor is used.
Generally Fly-back and SEPIC type converters can be noisy because of there power demand is pulsed current. With SEPIC it is necessary to think about the PCB layout to ensure that power and power switching tracks are optimal once you see it you see they do fall the right way for you (that is the art bit of electronics, and it is not worth being expedient). http://www.coilcraft.com/pdfs/doc639_Selecting_SEPIC_Inductors.pdf
SHOOT through noise and the risk of both transistors turning on;
The transistors in a half bridge configuration would introduce shoot through noise if both transistors were to be switched on at the same time, just briefly. This very high current pulse must be avoided.
The usual solution is to have short dead time when neither transistor is turned on. The problem with this is that stray inductance will cause a pulse of electrical interference. The Schottky diodes partly deal with this by ensuring the pulse wave form is small and is clamped cleanly, and therefore does not overshoot and cause ringing. A better or additional method is to add RC snubber to dampen the pulse as shown above
There is a similar effect in which miller capacitance couples a pulse into the gate or base input of the transistor or SCR. This can be a big problem with IGBT, once again the snubber helps in that it will slow the edges of the waveform. SCR's latch on with high voltage or high dV/dT, but this causes fuses to blow, but in any other semiconductor generally fails first.
In the case of larger transistors and any SCR particularly, the drive must be fast and there is a minimum gate current which ensures that the whole SCR passes the current rather than areas becoming hot spots and fuse. This may be less of an issue though with MOSFET transistors because of their positive thermal coefficient would tend to pass less current in the hot spot.
See more on thyristors triacs below - these used to be used and could produce a lot of electrical interference. So most of those applications have changed and use other strategies.
Learning lessons from older technology
SCR Manual Fifth Edition by General Electric of 1972 has a number of old but very good solutions for the design problems for sine wave and other inverters; They particularly solve the problem of switching the semiconductor off that remains difficult. Those designs use many discrete semiconductors and wound components plus quite elegant design solutions as was common for the time when switch mode power supplies IC's had not been invented yet (SGS 1976). The SCR Manual shows some elegant designs that turn the thyristors off by using a second thyristor to applying a negative pulse to the current carrying thyristor and thereby cause it to be turned off such a technique could not be applied to any transistor type because they can not stand a large negative voltage pulse, but the circuits are still worth considering because another solution may come to mind?
I have a copy and have successfully demonstrated to myself induction heating using two thyristors in half bridge configuration perhaps running at <20KHz - I can't remember now but this was in the late 1970s. I have also experimented with the other inverters shown but using transistors but in a different configuration and recall that if I did not figure it out some very high current would unsolder my diodes but did not break them. Gate Turn Off Thyristors work successfully in a common gate configuration with an LT1070 driving the cathode - even though I had prototyped with Vero-board using there would have been a Resistor+Capacitor+Diode snubber on the Anode and a snubber network on the main supply.
As with driving thyristors or transistors, it is also important to clamp the input Gate or Base to 0V when turning the semiconductor off in order to maximise speed and minimise the risk of damage due to slow turning off or false turn on of the semiconductor. Power BJT's switch off faster, I am advised by a Philips applications engineer in about 1985, if the base is driven into reverse breakdown. I show some theoretical examples in the next page.
I have used a thyristor as an overvoltage protection in this blog bicycle-hub-dynamo-maintanance-project at the bottom of the page.
Page 3 left-hand side. Crowbar overvoltage protection will switch off when the current falls to zero, so that does not prevent the circuit working but does prevent damage to the circuit.
How it saves power works;
The generator outputs, 300mA
If the voltage were simply clamped to 40V then the power wasted would be up to; 12W = 300mA x 40V
The two diodes represent duplicates in parallel of the top two diodes of a bridge rectifier. When the SCR turns on, the total voltage drop is; 2.5V = 1.5V (SCR) + 1V (two diodes).
Therefore, the wasted power is only up to; 750mW = 2.5V x 300mA.
My Blog for discussion - based on a working example; Electronics - high-frequency metal-vapor-arc-lamp power supply
To discuss electronics on this page, see; Blog page Electronics